1. Field of the Invention
The present invention relates to a package substrate manufactured using an electrolytic leadless plating process, and a method for manufacturing the same. More particularly, the present invention relates to a package substrate of, for example, a ball grid array (BGA) type or a chip scale package (CSP) type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers to be connected with a semiconductor chip mounted on a base substrate, and solder ball pads, and a method for manufacturing the same.
2. Description of the Related Art
In spite of the recent tendency of integrated circuits to have a light, thin, simple and miniature structure, integrated circuit packages rather tend to have an increased number of leads extending outwardly therefrom. One method capable of solving problems caused by installation of a number of leads on a carrier for a miniature package is to use a carrier having a pin grid array (PGA). Although such a PGA carrier can have a number of leads while having a miniature size, it has a drawback in that its pins or leads may be easily broken due to their low strength, and there is a limitation to its high-density integration.
In order to solve such drawbacks involved with PGA, use of BGA package substrates has recently been generalized. The reason why such a BGA package substrate has been generally used is that it is possible to easily achieve a high-density integration of the substrate in accordance with use of solder balls finer than pins. Such a BGA package substrate is mainly used for a package substrate adapted to mount a semiconductor chip thereon.
A conventional example of such a BGA package will be described in brief hereinafter. Referring to FIG. 1, a conventional BGA package is shown which has a structure formed with solder balls 8, in place of conventional pins. In order to fabricate this structure, a plurality of copper clad laminates (CCLs) 4 are first prepared. An inner-layer circuit is formed at each of the CCLs 4 in accordance with a well-known photolithography process. The CCLs 4 are then laminated in accordance with a pressing process. Thereafter, via holes 2 are formed at the laminated CCL structure in order to electrically connect the inner-layer circuits of respective CCLs. The via holes 2 are plated with a copper film 3 so that they are electrically connected. An outer-layer circuit 6 is subsequently formed at the outermost CCL 4 of the laminated CCL structure in accordance with a photolithography process. The outer-layer circuit 6 has bond fingers 1 to be connected with a semiconductor chip mounted on the laminated CCL structure. Thereafter, solder ball pads 7, a solder mask 5, and solder balls 8 are sequentially formed at a surface of the laminated CCL structure opposite to the outer-layer circuit 6.
Meanwhile, Au-plating lead lines are formed in order to perform a plating process adapted to obtain improved electrical connections of the pads 7 with both the bond fingers 1 connected to the semiconductor chip and the solder balls 8. Each Au-plating lead line is connected to an associated one of the pads 7 connected to respective solder balls 8. Although not shown, the Au-plating lead lines are also connected to the bond fingers 1 via the pads 7 and via holes 2, respectively. FIG. 2 is a plan view illustrating the package substrate plated using conventional plating lead lines. As shown in FIG. 2, plating lead lines 9 are connected to respective solder ball pads 7 at which respective solder balls 8 are formed. The area where the plating lead lines 9 are formed corresponds to the portion A of FIG. 1. Substantially, there is a limitation to high-density integration in designing a circuit, due to such plating lead lines.
On the other hand, an integrated circuit (IC) chip is mounted on the CCL 4 formed with the outer-layer circuit 6, while being connected with the outer-layer circuit 6 by conductive lines. An encapsulant is coated over the CCL 4 to protect the CCL 4 from the surroundings. Thus, the BGA package substrate 10 is connected with a main circuit board by the solder balls 8 formed at the pads 7 of the pad-carried CCL 4, as compared to a PGA substrate which is connected to a main circuit board by pins. For this reason, it is possible to easily miniaturize BGAs, as compared to PGAs. Accordingly, the BGA substrate 10 can achieve high-density integration.
However, the above mentioned conventional BGA package substrate 10 involves a problem in that it is difficult to achieve high-density integration of the Au-plating lead lines adapted to carry out an Au plating process for the bond fingers 1 and pads 7 because the pitch of the solder balls 8 in the BGA package substrate, that is, the space between adjacent solder balls, is rendered to be very small due to high-density integration of circuits and miniaturization of devices using such circuits, and because of high-density integration of circuits arranged around the bond fingers 1 of the outer-layer circuit mounted with the semiconductor chip thereon.
Now, a conventional method for manufacturing a package substrate plated with Au using plating lead lines will be described with reference to FIGS. 3a to 3f. 
In order to manufacture a package substrate provided with desired circuits, dry films 15 are first coated over upper and lower surfaces of a base substrate, a CCL. Each dry film 15 is then subjected to exposure and development processes, so that it is patterned to have a desired pattern for formation of a desired circuit. The CCL includes an insulator 11, and copper foils 12 respectively coated over upper and lower surfaces of the insulator 11. Practically, the patterning of the dry films 15 for formation of desired circuits is carried out after completion of processes for forming via holes 13 at the CCL by use of a mechanical drill, and plating a copper film 14 covering each copper foil 12 and each via hole 13.
Thereafter, the copper films 14 and copper foils 12 are partially etched, using the patterned dry films 15 as etch resists. That is, exposed portions of the copper films 14 and copper foils 12 are removed by an etchant, thereby forming desired circuits (FIG. 3b). In this etching process, plating lead lines to be used in a subsequent Au plating process are also formed. In FIG. 3b, the reference numeral 16 denotes a region where exposed copper is etched.
After completion of the etching process, the dry films 15 used as etch resists are removed using a stripping solution (FIG. 3c).
A solder resist 17 is then coated over the entire exposed surface of the resultant structure. The solder resist 17 is patterned in accordance with exposure and development processes, and then dried (FIG. 3d).
An Au film 18 is plated on wire bonding pads and solder ball pads included in respective circuits by applying current to the previously formed plating lead lines. The plating of the Au film 18 may be achieved in accordance with an electrolytic Ni—Au plating process. Typically, the thickness of the plated Au film 18 is about 0.5 to 1.0 μm (FIG. 3e).
Generally, an electrolytic Au plating process is mainly used for metal finishing of the surface of a package substrate on which a semiconductor chip is mounted, because it is superior over an electroless Au plating process, in terms of reliability. For such an electrolytic Au plating process, however, it is necessary to design the package substrate to be provided with plating lead lines. For this reason, there is a reduction in line density. Such a reduced line density causes a problem in manufacturing a circuit having a high-density integration.
Thereafter, the plating lead lines are cut using a router or a dicing process (FIG. 3f). In FIG. 3f, the reference numeral 19 denotes a region where the dicing process is carried out. That is, the plating lead lines are cut using the router or dicing process, after completion of the electrolytic Au plating process. However, the plating lead lines are incompletely removed from the package substrate. The residues of the plating lead lines may cause noise during transmission of electrical signals in the circuits provided at the package substrate. As a result, there is a degradation in electrical performance.